The present invention relates to CCD and CMOS image sensors, and specifically to charge detection circuits for the CCD image sensors that have high Dynamic Range (DR) and low reset feed through.
A typical image sensor senses light by converting impinging photons into electrons that are integrated (collected) in the sensor pixels. After the integration cycle is completed, charge is converted into a voltage that is supplied to the output terminals of the sensor. The charge to voltage conversion is accomplished either directly in the sensor pixels, such as in the Active Pixel CMOS sensors, or remotely off the sensing area, in charge conversion amplifiers. The most popular circuit used in these amplifiers consists of a Floating Diffusion (FD) charge detection node coupled to a source follower and reset by a reset transistor to a suitable reference voltage. The detail description of such an amplifier can be found for example in the book: xe2x80x9cSolid-State Imaging with Charge-Coupled Devicesxe2x80x9d by Albert J. P. Theuwissen pp. 76-79, published in 1995 by Kluwer Academic Publishers.
The FD charge detection concept has many advantages such as simplicity of design, simplicity of operation, high charge to voltage conversion factor, and a well-established technology know how. However, the two main disadvantages are kTC noise and a large reset feed through. kTC noise has been significantly reduced over the years by developing the Correlated Double Sampling (CDS) signal processing technique, but not much progress has been made to date with the reset feed through problem. The reset feed through results from a capacitive coupling of the reset gate to the FD charge detection node. The reset gate must be pulsed with a relatively large pulse to remove charge from the node after sensing and this introduces an undesirable pulse into the output signal. The problem is further exacerbated by the recent demands for large charge conversion factors that necessitate reduction in the overall FD node capacitance. Since it is difficult to correspondingly reduce the FD node to reset gate capacitive coupling, the minimum value has already been reached, the over all node capacitance to the coupling capacitance ratio thus becomes much worse. A poor ratio of these capacitances then increases the feed through and as a result significantly reduces the useful voltage swing that can be allocated for the signal. It is therefore desirable to develop a new method for resetting the FD charge detection node that does not introduce the large reset feed through. By developing such a method, it is then possible to significantly increase the charge conversion sensitivity, and, at the same time, allocate a larger voltage swing for the signal resulting in higher Dynamic Range.
The present invention achieves high dynamic range readout capability. The prior art does not show how to use the Transistor Punch Through (TPT)concept for the Floating Diffusion, or Floating Gate CCD well reset, or how to design the reset circuit that has a small reset feed through and as a consequence high DR. The prior art does not teach that the incomplete reset caused by the charge flow over the barrier in the TPT reset concept when applied to the FD node can be reduced to an undetectable minimum by incorporating the CDS signal processing technique. The prior art does not teach that the reset circuit time constant in standard FD charge detection node can be comparable to the reset time period.
The invention is based on a Transistor Punch Through (TPT) concept that is used for resetting the Floating Diffusion (FD) or the Floating Gate (FG) charge detection nodes instead of the more conventional transistor gate resets. The incorporation of the TPT concept leads to an increase in the maximum voltage swing that is permissible on the FD and FG charge detection nodes by reducing the reset gate pulse capacitive coupling to the node. The undesirable effects of incomplete reset, inherent in the TPT concept used with the FD, are reduced to an undetectable minimum by using the well-known Correlated Double Sampling (CDS) signal processing technique.
The present invention provides a practical high DR charge detection node that has a small reset feed through, and provides a practical high performance low reset feed through charge detection circuit that uses Correlated Double Sampling to minimize the unwanted effects of incomplete reset. These features are achieved by replacing the conventional reset transistor, typically used in the standard Floating Diffusion charge detection nodes, with a Transistor that operates in a Punch Through mode. In the TPT reset mode of operation, the reset pulses are not applied to the transistor gate, but are applied to the transistor drain, while the gate is held at a suitable DC bias, preferably ground. This feature provides an efficient shielding and decoupling of the reset pulses from the FD or FG node. The transistor drain may also serve as an Output Diode (OD) to collect charge from the CCD register.
In another embodiment of the present invention, the TPT reset transistor structure has a dual gate. The gate adjacent to the FD node is short and held at a suitable DC bias. The reset pulses are applied to the second larger gate, which causes the potential under the short gate to also rise, which further causes reset by removing charge from the FD node. The drain in this structure is biased at a large DC bias such as Vdd. Since charge in both of these embodiments is removed by flowing over a barrier rather than by an equilibration of Femi Levels of the FD and OD nodes, no equilibrium is ever reached, and the reset process is thus incomplete. It is well known that the incomplete reset of charge detection nodes causes many artifacts in the sensor image. This would be a large drawback for the TPT reset approach that would make it virtually unusable in many high performance-imaging applications. Fortunately, the well-known CDS signal processing technique, which was developed to minimize kTC noise, is also effective here and efficiently removes all the artifacts of the incomplete reset. Further, more the CDS technique can be extended to any charge detection circuit that has the reset time constant comparable to the reset time period.
In another embodiment of the invention, the FD node is replaced by a CCD well that exists, for example, under the Floating Gate charge detection node and the PT reset is used to remove charge from this well. In this case the charge removal from the well is complete and no CDS signal processing has to be used.
The TPT reset technique thus allows design of high performance charge detection systems that are free of all artifacts, have high charge conversion factors, small reset feed through, and high dynamic range. The high dynamic range results from the large available output signal swing that is not reduced by the reset feed through, as is the case, for example, in conventional FD charge detection structures.